On AVR: ~80 cycles = 5 microseconds. On ARM: 1 cycle (MUL instruction). ### Pipeline Hazards (ARM Cortex-M3) Three-stage pipeline: fetch, decode, execute. 1. **Data hazard**: bypass logic in hardware 2. **Control hazard**: Branch instruction flushes pipeline 3. **Structural hazard**: Harvard architecture mitigates via separate code/data buses ### Register Allocation For ARM (13 general registers): - R4-R11 are callee-saved (preserved across function calls) - R0-R3 are argument/return registers - R12 is intra-procedure call scratch ### Limiting Cases - **8-bit MCU with 32-bit computation**: Each 32-bit operation requires 4+ instructions - **No FPU**: Floating-point operations emulated in software (hundreds of cycles per op) - **Tiny RAM (< 256 bytes)**: Cannot use C standard library functions `c // AVR register-level access vs ARM // AVR ATmega328P #define DDRB (*(volatile uint8_t *)0x24) #define PORTB (*(volatile uint8_t *)0x25) void avr_gpio_example() { DDRB |= (1 << 5); PORTB |= (1 << 5); } // ARM Cortex-M STM32 #define GPIOA_MODER (*(volatile uint32_t *)0x40020000) #define GPIOA_BSRR (*(volatile uint32_t *)0x40020018) void arm_gpio_example() { GPIOA_MODER &= ~(3 << 10); GPIOA_MODER |= (1 << 10); GPIOA_BSRR = (1 << 5); } ` [[SIM:ArchitectureExplorer]] **Simulation -- ArchitectureExplorer** | Field | Detail | |---|---| | Render type | 2D Interactive CPU Datapath | | ME domain | MCU Architecture | | User inputs | 1. Select AVR or ARM Cortex-M4
2. Step through assembly instructions
3. View register file and pipeline stages | | Primary visual | CPU datapath diagram with animated data flow | | Secondary output | Instruction cycle count and execution time | | "Aha" moment | Stepping through 32-bit multiply on AVR (80 cycles) vs. ARM (1 cycle) shows the performance gap visually | ## Worked Examples ### Example 1 -- Foundational (MCU Selection) Select an MCU for a digital oscilloscope: 100 MS/s sample rate, 8-bit resolution, TFT display, USB. **Selection**: STM32F407 (ARM Cortex-M4F, 168 MHz) - 2x 12-bit ADC (2.4 MS/s) using interleaved mode - DMA for automatic data transfer ADC->buffer - 192 KB RAM for sample buffer - Built-in USB OTG **Not suitable**: ATmega328P (too slow, too little RAM, no DMA) ### Example 2 -- Industry-Grade (Startup Code) ARM Cortex-M startup sequence: 1. Reset vector loads SP from 0x0000, Reset_Handler from 0x0004 2. Reset_Handler calls SystemInit() for clock configuration 3. Copy .data from flash to SRAM 4. Zero-initialize .bss section 5. Call constructors for static C++ objects 6. Call main() `c extern uint32_t _estack; extern uint32_t _sdata, _edata, _sidata; extern uint32_t _sbss, _ebss; void Reset_Handler(void) { uint32_t *src, *dst; src = &_sidata; dst = &_sdata; while (dst < &_edata) *dst++ = *src++; dst = &_sbss; while (dst < &_ebss) *dst++ = 0; main(); } ` ## Common Misconceptions & Failure Modes - **Wrong belief**: Higher clock speed always means better performance. - **Correct framing**: Architecture matters more. An 8-bit AVR at 20 MHz is far slower than ARM Cortex-M0 at 48 MHz for 16/32-bit operations. - **Real failure mode**: Stack overflow on a small MCU. Stack grows down, heap grows up -- they collide. Use static allocation only. ## Professional Engineering Insight In automotive ECUs, dominant architectures are Infineon TriCore and NXP S32K (ARM Cortex-M). These have lockstep cores for safety, hardware security modules, and ASIL-D certification. A modern car has 50-100 MCUs. ## Practice Problems **P1**: Compare execution time for 32x32-bit multiply on 8-bit AVR (16 MHz), ARM Cortex-M0 (48 MHz), and Cortex-M4 (168 MHz with single-cycle MAC). **P2**: A system requires 64 KB code, 16 KB RAM, 8 analog inputs, 1 ms interrupt latency, USB device. Propose two MCU families. **P3**: What happens if the stack pointer is initialized to an invalid address? What if Reset_Handler points to 0xFFFFFFFF (unprogrammed flash)?